Advanced integrated circuits commonly employ microelectronic devices that are wired on different conductor levels. The conductor levels of these devices are electrically isolated from each other by thin dielectric insulating layers. Contact studs are employed to electrically couple selected conductor levels together. Generally, the contact studs pass through contact holes which extend through the thin dielectric insulating layers and/or other conductor levels. Such contact structures are fabricated by etching the contact holes into the insulating layers during circuit fabrication and then filling the contact holes with metallization prior to deposition and patterning of the next conductor level.
An example of such a contact structure is depicted in FIG. 1A. As can be seen, adjacent conductor levels 10 and 14 are electrically coupled to each other by a contact stud 16 which passes through a thin dielectric insulating layer 12. In this example, the contact stud is surrounded by the thin dielectric insulating layer and are often referred to in the art as a bordered contact.
Another type of contact structure is depicted in FIG. 1B, where a patterned conductor level 24 having spaced apart conducting segments 26 and 28, which for example may represent the gates of a transistor, are present between an upper conductor level 20 and a lower conductor level 34. The contact stud 36 in this example extends between the conducting segments 26 and 28 of the patterned conductor level 24. The contact stud 36, where it passes between the conducting segments 26 and 28, is electrically isolated from the patterned conductor level 24, by a thin dielectric insulating layer 30. Such a contact structure is often referred to in the art as a self-aligned borderless contact. Self-aligned borderless contacts provide a maximum contact area while minimizing the spacing required between the patterned conducting segments (gates) through which they pass. Thus, self-aligned borderless contacts increase the package densities of advanced integrated circuits. Accordingly, self-aligned borderless contacts are often used for submicron device fabrication.
Ideally, the self-aligned borderless contact shown in FIG. 1B, can be fabricated as follows. A first dielectric insulating layer 22 is deposited over the lower conductor level 20. The conductor level 24 is then deposited over the first dielectric insulating layer 22 and patterned to create the conducting segments 26 and 28. Next, the second dielectric insulating layer 30 is deposited over the conducting segments 26, 28 and then covered by depositing a third dielectric insulating layer 32. The third dielectric insulating layer 32 is subsequently planarized so that the upper conductor level can be deposited thereon in a later processing step. A self-aligning contact hole etching process is used to fabricate a contact hole in the third dielectric insulating layer 32 between the conducting segments 26 and 28. Such a process is accomplished by lithography and anisotropic etching techniques. The self-aligning etching process has to be selective to the first dielectric insulating layer 22 to protect the first conductor level 20 from uncontrolled etching or thinning and selective to the second dielectric insulating layer 30 to avoid a breaking through to the conducting segments 26 and 28. The final width of the contact hole in a self-aligning process is determined by the spacing between the conductor segments 26 and 28 in the patterned conductor level 24 shown in FIG. 1B. Next, an anisotropic etch is performed to extend the contact hole through the second dielectric insulating layer 30 and the contact stud 38 is formed by filling the contact hole with a conductor material.
There are, however, problems associated with the actual practice of the self-aligning contact hole etching process described above. In particular, during the etching of the contact hole, the corner of the conducting segments 26 and 28 are exposed to the etchant. This is due to the fact that the etching process actually generates a contact hole opening which is somewhat larger than the spacing between the conducting segments 26 and 28. This result occurs because the etch rate at a corner structure is much higher than the etch rate for a planar surface structure (up to 7 times higher), hence, the corners of the conducting segments can erode during the contact hole etch process. This remains the case even when materials with very high etch selectivity are employed, like polysilicon as an etch stop and/or BPSG as a dielectric.
For example, in the example shown in FIG. 1B, the selectivity of the anisotropic etching between third dielectric insulating layer 32 and the substantially thinner second dielectric insulating layer 30 is often not sufficient to provide a reliable etch stop at the second dielectric insulating layer 30. Typical thickness ratios between the third dielectric insulating layer 32 and the second dielectric insulating layer 30 are often greater than 10 to 1. Thus, in actual practice the prior art has attempted to solve the corner erosion problem, as shown in FIG. 1C, by providing an additional etch stop layer 38 between the third dielectric insulating layer 32 and the second dielectric insulating layer 30. As shown, the etch stop layer 38 is a doped polysilicon layer which is conductive. The polysilicon layer has a very high etching selectivity to the oxide of the third dielectric insulating layer 32. After the etching, the polysilicon layer 38 is oxidized and transformed into an insulating layer.
The solution described above still has its problems.
In particular, when the polysilicon etch stop layer 38 is oxidized into the insulating layer, stresses are created which can cause device failures. Further, residuals of unoxidized polysilicon tend to remain after the oxidation process which causes shorts or high leakage in the second conductor level.
In response to the problems associated with the polysilicon etch stop layer, other prior art processes have been developed which employ aluminum oxide (Al.sub.2 O.sub.3) instead of polysilicon to avoid the problems associated with oxidizing polysilicon. This is because Al.sub.2 O.sub.3 is already an insulating layer and hence, no oxidation process is necessary. Substituting Al.sub.2 O.sub.3 for polysilicon has one major disadvantage in that Al.sub.2 O.sub.3 is difficult to etch.
Other prior art techniques have also been developed to prevent the gates from eroding during the etch process. One such process employs Si.sub.3 N.sub.4 as an etch stop to take advantage of the selectivity between the SiO.sub.2 and Si.sub.3 N.sub.4. This process requires depositing a thick nitride cap and a nitride liner between the third dielectric insulating layer 32 and the second dielectric insulating layer 30. The etch process is carried out in a high density plasma reactor with decreased ion bombardment and reduced gas flow. During the process a polymer is generated on the sidewalls of the conducting segments to prevent chemical reaction.
Problems, however, are still associated with this technique. In particular, the selectivity to nitride at the corners is drastically reduced. Consequently, a novel etch tool is required to achieve the required selectivity. Polymer formation on the nitride is required for selectivity, but polymer can also form on the bottom of the hole and stop the etch.
Another process which has been proposed for preventing the gates from eroding during the contact hole etch process involves the fabrication of spacers in area of the contact holes. The spacer process involves a two step contact etch. The first etching step involves an anisotropic etch. Next, a polysilicon sidewall spacer is formed in the area of the contact hole which prevents the conducting segments from eroding during a second anisotropic etch which opens the contact holes.
A major problem with this technique is that the polysilicon spacers reduce the area of the contact holes which in turn, reduces the size of the contact studs.
It is, therefore, an object of the present invention to provide an improved self aligning contact hole etching method which substantially prevents the erosion of the conducting segments.